With aggressive scaling of the FinFET technology design rule, use of a gate cut (CT) pillar for gate (PC) isolation becomes increasingly challenging. In particular, the CT pillar must land between trenches and allow enough room for work function (WF) metal to be subsequently formed on the sides of the device fins. A known approach for using a CT pillar for PC isolation involves forming carbon spacers in amorphous carbon (a-C) and silicon oxynitride (SiON) layers of a CT lithography stack. Another known approach involves forming trenches in an amorphous silicon (a-Si) layer and then filling the trenches with silicon nitride (SiN). However, with respect to both approaches, the WF metal of the CT pillar often merges with the WF metal at the edge of an adjacent fin, resulting in threshold voltage (Vt) variation and/or the CT pillar to active fin (RXFIN) critical dimension (CD) is insufficient for proper formation.
A need therefore exists for methodology enabling formation of a small CT pillar without overlay or fin merger issues and the resulting device.